This invention relates to wire scribed circuit boards, multilayer printed circuit boards and circuit boards for chip carrier using a heat resistant resin adhesive composition for the insulating adhesive layers, and processes for producing these circuit boards.
The wire scribed circuit boards have a structure in which the adhesive layers are provided on the substrates, and a plurality of wires having an insulating coating for forming conductor circuits are scribed and fixed in said layers, with the interlayer connections being made by through holes, and such circuit boards are disclosed in U.S. Pat. Nos. 4,097,684, 3,646,572, 3,674,914 and 3,674,602. They are known as the printed circuit boards which are capable of high-density wiring and advantageous for matching of characteristic impedance and reduction of crosstalks.
In the prior art, insulation resistance of the circuit boards was well within the range of permissible error for the conventional wiring density, and posit- ional precision of wires was also acceptable for practical use because of low wiring density and large hole size although there would usually be observed wire swimming of approximately 0.2 mm against the design value after wiring, lamination and bonding of the printed circuit boards.
However, increase of wiring density such as seen in recent years may lead to an excessive reduction of insulation resistance when a rubber-based adhesive is used for bonding. Also, higher wiring density entails smaller hole size, and further, enlargement of wire swimming tends to cause displacement of the insulating coated wires at the positions where through holes are to be formed, giving rise to the problem of improper wire connection.
As a solution to this problem, UV curing adhesive sheets using a phenol resin, an epoxy resin, an epoxy-modified-polybutadiene or the like as adhesive, such as disclosed in JP-B-5-164525, have been proposed. In the conventional methods, prepregs have been laminated after fixing the wires having an insulating coating. In these methods, since wire swimming is enlarged when prepregs are laminated after wiring by use of said type of adhesive, it is tried to control wire swimming by adding a preliminary curing step between the wiring step and the laminating step to cause a slight degree of curing of the adhesive layer. However, increase of the laminations has posed the problem of reduced solder heat resistance because of the enlarged difference in thermal expansion coefficient between the prepreg or substrate and the adhesive at the glass transition point or above.
On the other hand, the multilayer printed circuit boards usually comprise an interlayer substrate containing a power source layer and a ground layer, a plurality of prepreg layers having circuit conductors thereon on the surface of the interlayer substrate, via holes for electrical connection of only necessary circuit conductors, plated-through holes for electrical connection of necessary circuit conductors through all the laminated layers, and a solder resist for insulating the surface circuits.
Many methods are known for producing such multilayer printed circuit boards. A typical and commonly known method comprises the steps of etching away unnecessary portions of a copper foil of a copper-clad laminate to form internal circuits and interlayer substrate which constitutes a power source layer and a ground layer, placing thereon prepregs and copper foils and pressing them with heating for integral lamination, etching away unnecessary portions of the copper foil and repeating the placing of prepregs and the circuit formation for required times, drilling holes in portions necessary for electrical connection, metallizing the inner walls of said holes by electroless plating or other appropriate means, etching away unnecessary portions of the surface copper foils, and coating a solder resist, followed by drying.
A method is also well known in which the interlayer substrates for the respective layers are separately produced, and after positioning with guide pins, these substrates are integrally laminated and drilled to form through holes, followed by formation of surface circuits and a solder resist.
The recent tendency toward smaller size, higher performance and multiplication of functions of electronic devices has further prompted the effort for realizing higher wiring density of the multilayer printed wiring boards. Such efforts for attaining higher wiring density have materialized further reduction of interlayer thickness, wire size and interlayer connecting hole diameter, and use of interstitial via holes (IVH) which connect the adjoining wiring layers alone. Reduction of size of IVH and multiplication of layers are now required for attaining higher density of the wiring boards.
A built-up wiring board of a structure in which the insulating layers and the conductor circuits are laminated alternately on the outer surface of an interlayer substrate has been proposed as an example of printed circuit board of a multilayer structure.
A commonly practiced procedure for producing the built-up wiring boards is shown here. On the outer surface of an interlayer substrate having the interlayer circuits thereon is formed an insulating layer, which is the first layer of the laminate, by coating and curing an adhesive for additive.
The "adhesive for additive" means an adhesive for forming conductor circuits on the surface thereof by electroless plating.
Then the holes for forming IVH are formed at the necessary portions of the insulating layer by laser beam drilling, wet etching or photo etching method.
Laser beam drilling is a technique for making holes by applying laser beams to the pertinent spots of the insulating layer to cause evaporation of the layer material at the spots. Wet etching is a method in which the pertinent portions of the insulating layer are etched away with a chemical etching solution. Photo etching method is a method in which the pertinent portions of the insulating layer are selectively photocured, with the other portions removed by development.
A surface roughening treatment is carried out on the interlaminar insulating layer, and a catalyst for depositing electroless copper plating is applied to the roughened surface to form a thin deposit of electroless copper plating. Then the current paths for performing electroplating are formed and electroplating is carried out thereon to a necessary thickness to form an etching resist. The portions where no etching resist has been formed are selectively removed by etching to form outer layer wiring.
The interlaminar insulating layer and conductor layer forming the second layer can be formed basically by repeating the process of the built-up board producing method described above.
Reduction of the insulating layer thickness has been proposed for realizing thickness reduction of the multilayer printed circuit boards. There is a limitation on the degree of thickness reduction that can be achieved when prepregs containing reinforcements such as glass cloth are used for the insulating layers, so a resin sheet containing no glass cloth or like reinforcements has recently been developed as an improved insulating layer.
When plating is conducted on a recessed portion such as IVH, there is formed a depression in the middle of IVH, and if the second built-up layer is formed with said depression left, unevenness is produced on the substrate surface to make a substrate poor in flatness, resulting in a reduced bonding precision in mounting of parts or shortcircuiting or disconnection of lines in the wiring step.
Also, increase of the layers containing no reinforcements such as glass cloth in the PC boards gives rise to the problem that voids tend to be formed in the interlaminar insulating layers or separation thereof tends to take place due to the difference in glass transition point, linear expansion coefficient or storage elastic modulus between said insulating layers and the interlayer substrates.
Regarding the semiconductor chip packages, JP-A-59-158579 taught a structure in which the terminals connected to the semiconductor chips are led out from the inside to a part on the outside of the package to constitute a leadless chip carrier.
Also, JP-B-58-11100 disclosed a pin grid array having a plurality of rows of terminal pins for connection to the through holes in the other package-mounting boards, and a process for producing such a pin grid array.
JP-B-58-11100 also disclosed a ball grid array in which the balls are fused and soldered to the lands, in place of the pins in pin grid arrays, to thereby make electrical connections.
Further, JP-B-58-26828 proposed to initially form the terminals and then insulate tape-like films to constitute an automated tape carrier.
In these semiconductor chip packages (hereinafter referred to as "wiring boards for chip carriers"), ceramic materials have been popularly used as insulator, and semiconductor chip terminals were electrically connected to these chip carriers by wire bonding. organic insulating materials have been used as sealant for protecting the semiconductor chips or the connected portions from environmental attack after mounting of the semiconductor chips on said chip carriers.
Further, in recent years, in view of poor economy of use of conventional ceramic materials for chip carriers because of the increased number of calcination steps, the chip carrier producing methods utilizing the so-called multilayer wiring board manufacturing techniques using an organic insulating material have been developed. For example, JP-B-3-25023 disclosed a method for producing pin grid array packages using an organic insulating material.
In the field of wiring boards for chip carriers, too, there has recently been increasing request for size reduction and functional multiplication of the electronic devices, and the necessity for higher density of wiring and size reduction has become intense. Slimming has also been required for the insulating material used for the insulating adhesive layers interposed between the interlayer circuits, and it has now become hardly possible for the conventional prepregs to adapt themselves to the desired thickness of glass fabric or nonwoven cloth used therefor. This has prompted the attempts to coat an insulating resin or to make a film thereof.
However, use of a prepreg containing no reinforcement such as glass fabric or nonwoven fabric for the insulating adhesive layers has a tendency to encourage formation of voids in or peeling of the insulating adhesive layers, giving rise to the problem of unreliability of connection or lowering of solder heat resistance.